Synchronous multi-thread processor

A synchronous multi-thread processor comprises an index RAM (random access memory), a storage buffer, a data cache and at least two assembly lines; the at least two assembly lines are respectively connected with the index RAM, the storage buffer and the data cache and are suitable for accessing the data cache. Each assembly line has a one-to-one corresponding data cache region, and the data cacheregions are used for storing a part of data corresponding to the data storage instruction when the digit of the to-be-stored data received by the corresponding assembly line is greater than the maximum data digit of the corresponding assembly line; and the data shifter is suitable for shifting the data in the data cache regions corresponding to different assembly lines so as to recover the to-be-stored data, and storing the to-be-stored data into the storage cache. According to the scheme, while real-time storage of the data is realized, a pipeline with a lower bit number is used for supporting a processor with a high