Resistive random access memory device, writing method, erasing method and reading method of resistive random access memory device

The invention discloses a resistive random access memory device. The device comprises a field effect transistor, a bit line, a word line and a source line; the drain of the field effect transistor isconnected with the bit line; the grid of the field effect transistor is connected with the word line;...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: CAI YIMAO, XIAO HAN, LIU YIHUA, WANG ZONGWEI
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator CAI YIMAO
XIAO HAN
LIU YIHUA
WANG ZONGWEI
description The invention discloses a resistive random access memory device. The device comprises a field effect transistor, a bit line, a word line and a source line; the drain of the field effect transistor isconnected with the bit line; the grid of the field effect transistor is connected with the word line; the source of the field effect transistor is connected with the source line; the bit line comprises a plurality of dielectric layers, a lower electrode and an upper electrode which are arranged from bottom to top; a metal layer is clamped between every two adjacent dielectric layers; a plurality of resistive layers which are connected in parallel are arranged in the dielectric layers between the upper electrode and the lower electrode; and the upper end and lower end of each resistive layer are connected to the upper electrode and the lower electrode respectively; and a metal plug is arranged in each of the rest dielectric layers. According to the resistive random access memory device of the invention, the read cu
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN110620128A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN110620128A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN110620128A3</originalsourceid><addsrcrecordid>eNrjZGgMSi3OLC7JLEtVKErMS8nPVUhMTk4tLlbITc3NL6pUSEkty0xO1VEoL8osycxLBwqXZOSn6CikFiUWI_gKQK0KRamJKUhC-WlAESLM5mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hoYGZkYGhkYWjsbEqAEAoZpJsA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Resistive random access memory device, writing method, erasing method and reading method of resistive random access memory device</title><source>esp@cenet</source><creator>CAI YIMAO ; XIAO HAN ; LIU YIHUA ; WANG ZONGWEI</creator><creatorcontrib>CAI YIMAO ; XIAO HAN ; LIU YIHUA ; WANG ZONGWEI</creatorcontrib><description>The invention discloses a resistive random access memory device. The device comprises a field effect transistor, a bit line, a word line and a source line; the drain of the field effect transistor isconnected with the bit line; the grid of the field effect transistor is connected with the word line; the source of the field effect transistor is connected with the source line; the bit line comprises a plurality of dielectric layers, a lower electrode and an upper electrode which are arranged from bottom to top; a metal layer is clamped between every two adjacent dielectric layers; a plurality of resistive layers which are connected in parallel are arranged in the dielectric layers between the upper electrode and the lower electrode; and the upper end and lower end of each resistive layer are connected to the upper electrode and the lower electrode respectively; and a metal plug is arranged in each of the rest dielectric layers. According to the resistive random access memory device of the invention, the read cu</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20191227&amp;DB=EPODOC&amp;CC=CN&amp;NR=110620128A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20191227&amp;DB=EPODOC&amp;CC=CN&amp;NR=110620128A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CAI YIMAO</creatorcontrib><creatorcontrib>XIAO HAN</creatorcontrib><creatorcontrib>LIU YIHUA</creatorcontrib><creatorcontrib>WANG ZONGWEI</creatorcontrib><title>Resistive random access memory device, writing method, erasing method and reading method of resistive random access memory device</title><description>The invention discloses a resistive random access memory device. The device comprises a field effect transistor, a bit line, a word line and a source line; the drain of the field effect transistor isconnected with the bit line; the grid of the field effect transistor is connected with the word line; the source of the field effect transistor is connected with the source line; the bit line comprises a plurality of dielectric layers, a lower electrode and an upper electrode which are arranged from bottom to top; a metal layer is clamped between every two adjacent dielectric layers; a plurality of resistive layers which are connected in parallel are arranged in the dielectric layers between the upper electrode and the lower electrode; and the upper end and lower end of each resistive layer are connected to the upper electrode and the lower electrode respectively; and a metal plug is arranged in each of the rest dielectric layers. According to the resistive random access memory device of the invention, the read cu</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZGgMSi3OLC7JLEtVKErMS8nPVUhMTk4tLlbITc3NL6pUSEkty0xO1VEoL8osycxLBwqXZOSn6CikFiUWI_gKQK0KRamJKUhC-WlAESLM5mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hoYGZkYGhkYWjsbEqAEAoZpJsA</recordid><startdate>20191227</startdate><enddate>20191227</enddate><creator>CAI YIMAO</creator><creator>XIAO HAN</creator><creator>LIU YIHUA</creator><creator>WANG ZONGWEI</creator><scope>EVB</scope></search><sort><creationdate>20191227</creationdate><title>Resistive random access memory device, writing method, erasing method and reading method of resistive random access memory device</title><author>CAI YIMAO ; XIAO HAN ; LIU YIHUA ; WANG ZONGWEI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN110620128A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>CAI YIMAO</creatorcontrib><creatorcontrib>XIAO HAN</creatorcontrib><creatorcontrib>LIU YIHUA</creatorcontrib><creatorcontrib>WANG ZONGWEI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CAI YIMAO</au><au>XIAO HAN</au><au>LIU YIHUA</au><au>WANG ZONGWEI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Resistive random access memory device, writing method, erasing method and reading method of resistive random access memory device</title><date>2019-12-27</date><risdate>2019</risdate><abstract>The invention discloses a resistive random access memory device. The device comprises a field effect transistor, a bit line, a word line and a source line; the drain of the field effect transistor isconnected with the bit line; the grid of the field effect transistor is connected with the word line; the source of the field effect transistor is connected with the source line; the bit line comprises a plurality of dielectric layers, a lower electrode and an upper electrode which are arranged from bottom to top; a metal layer is clamped between every two adjacent dielectric layers; a plurality of resistive layers which are connected in parallel are arranged in the dielectric layers between the upper electrode and the lower electrode; and the upper end and lower end of each resistive layer are connected to the upper electrode and the lower electrode respectively; and a metal plug is arranged in each of the rest dielectric layers. According to the resistive random access memory device of the invention, the read cu</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_CN110620128A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
title Resistive random access memory device, writing method, erasing method and reading method of resistive random access memory device
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T18%3A39%3A32IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CAI%20YIMAO&rft.date=2019-12-27&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN110620128A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true