Electrostatic protection element layout structure with high electrostatic discharge tolerance

The invention discloses an electrostatic protection element layout structure with high electrostatic discharge tolerance. The structure comprises a plurality of NMOS transistors connected in parallel,wherein the NMOS transistors connected in parallel form an isolated NMOS multi-finger type semiconductor layout structure, a middle region of the isolated NMOS multi-finger semiconductor layout structure is a P-type doped region doped with high-energy P-type implanted ion concentration, so substrate resistance of the middle region is reduced. The structure is advantaged in that the total substrate resistance of the NMOS transistors corresponding to the middle region can be reduced, substrate resistance difference between the NMOS transistor corresponding to the middle region and the NMOS transistor corresponding to one of the NMOS transistors at two sides is reduced, so the NMOS transistors can be uniformly conducted, and the electrostatic discharge tolerance of the NMOS transistors is improved. 本发明公开了一种高静电放电耐受力的