Logic watchdog implementation method based on finite-state machine

The invention discloses a logic watchdog implementation method based on a finite-state machine, and the method comprises the following steps: a last-stage power supply of a single board being successfully powered on at 1.0 V, the state machine being switched from an initial state to a starting state, and starting a timer to start counting at the same time; when the CPLD detects the WDI output by the processor and the starting time is greater than or equal to 45s, switching the state machine from the starting state to the running state; and if the WDI signal is not detected when the starting time reaches 65s, switching the state machine from the starting state to the power-down state, at the moment, the CPLD outputting a 2s power-down signal to control other parts to be powered down, and then the state machine returning to the initial state. The finite-state machine is used for dividing system operation into an initial state, a starting state, an operation state and a power-down state,and the system operation