Chip structure for wafer-level wafer size packaging

The invention discloses a chip structure for wafer-level wafer size packaging, which comprises a packaging chip and at least two pin welding spots arranged on the surface of the packaging chip, wherein the pin welding spots are arranged on the edge of the packaging chip; the positions, adjacent to the edge of the packaging chip, of the pin welding spots are straight edges; and the positions, not adjacent to the edge of the packaging chip, of the pin welding spots are arc-shaped edges. Thus, the size of the packaged chip is further reduced by reducing the size of the pin welding spots, the chipintegration degree is improved, and the cost is reduced. 一种晶圆级晶片尺寸封装的芯片结构，包含封装芯片以及设置在封装芯片表面的至少2个引脚焊点，所述的引脚焊点设置在封装芯片的边缘，所述的引脚焊点与封装芯片的边缘相邻处的形状呈直边，所述的引脚焊点未与封装芯片的边缘相邻处的形状呈弧形边。本发明通过减小引脚焊点的尺寸来进一步减小封装芯片的尺寸，提高芯片集成度，降低成本。