Data packet processing method

The invention relates to a data packet processing method, which is operated in a circuit system such as a system on chip (SoC). The method includes: when a processor of the system wafer executes work,firstly, receiving and analyzing a data packet at least comprising key information; judging whether the data packet is a high-priority data packet or not according to an analysis result and the key information; if the data packet is a high-priority data packet, executing high priority interrupt processing (Rx High Priority Interrupt), sending an interrupt processing signal to a system end in realtime, otherwise, if the data packet is not a high priority data packet, judging that the data packet is a common data packet, executing interrupt regulation and control processing, and continuously receiving the data packet until a preset number or a preset time period is reached. The disclosed circuitry can maintain the instantaneity of the system to handle important tasks in addition to maintaining the characteristic of