ERROR CHECKING FOR PRIMARY SIGNAL TRANSMITTED BETWEEN FIRST AND SECOND CLOCK DOMAINS

The invention provides error checking for primary signal transmitted between first and second clock domains.An apparatus and method for transmitting signals between two clock domains in which at leastone of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain forreceiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain basedon the primary signal. Checking circuitryis provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interfa