ESD protection circuit in flyback primary feedback switching power supply control chip

The invention discloses an ESD protection circuit in a flyback primary feedback switching power supply control chip. The circuit is arranged on the FB end of a chip. The circuit comprises a semiconductor P-type substrate, a BN buried layer diffusing inside the P-type substrate, a P-well, an N-well, a high-concentration P-doped P+ implanted region and a high-concentration N-doped N+ implanted region, wherein the P-well and the N-well are formed on the upper surface of the BN buried layer. An isolation ring protection structure is provided when a switching power supply operates at negative voltage, which effectively avoids switch on of a parasitic transistor when voltage is negative. The ESD protection circuit clamps negative voltage to voltage Vss to VBE to protect low voltage devices of aninternal circuit. The ESD protection circuit is resistant to high voltages with the maximum withstand voltage of 48V. 本发明公开了一种反激式原边反馈开关电源控制芯片中的ESD保护电路，设置于芯片的FB端，包括半导体P型衬底，扩散在P衬底内部的BN埋层，形成于BN埋层上表面的P阱和N阱以及高浓度P型掺杂P+注入区和高浓度N型掺杂N