Transistor, gate structure and preparation methods thereof

The invention provides a transistor, a gate structure and preparation methods thereof. The gate structure comprises a wafer; a first passivation layer; the alignment mark layer which is provided with a window for detecting an etching end point of the gate groove; a second passivation layer; an implanted isolation layer which is disposed on the wafer and defines an active region; a gate trench layer, wherein one part of the gate trench layer is arranged in the active region, and the other part of the gate trench layer is provided with a window for detecting a grid groove etching end point and is positioned outside the active region; and a gate metal layer which is arranged on the gate trench layer. The preparation method of the gate structure comprises the following steps: obtaining a wafer, and depositing and generating a first passivation layer on the wafer; preparing an alignment mark layer at a specific position of one side surface of the first passivation layer; depositing and generating a second passivat