DVB-S2 standard-based LDPC code parallel decoding FPGA implementation architecture and decoding method

The invention discloses a DVB-S2 standard-based LDPC code parallel decoding FPGA implementation architecture and a decoding method. The DVB-S2 standard-based LDPC code parallel decoding FPGA implementation architecture mainly comprises a serial-to-parallel conversion module, an input cache module, a...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	ZHANG RUI, WANG BENQING, ZHAO FENG, MU HONGQIANG, HU JINLONG
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CODE CONVERSION IN GENERAL CODING DECODING ELECTRICITY
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