DVB-S2 standard-based LDPC code parallel decoding FPGA implementation architecture and decoding method

The invention discloses a DVB-S2 standard-based LDPC code parallel decoding FPGA implementation architecture and a decoding method. The DVB-S2 standard-based LDPC code parallel decoding FPGA implementation architecture mainly comprises a serial-to-parallel conversion module, an input cache module, a variable node updating module, an interleaver module, a node cache module and a check node updating module. Based on the quasi-cyclic characteristic of a DVB-S2 standard IRA-LDPC code, the two-dimensional interleaving can be realized only by performing the inter-column interleaving and intra-column cyclic shift on an intermediate calculation result during parallel decoding, and the two-dimensional operation is simplified into two one-dimensional operation. 本发明公开了一种基于DVB-S2标准的LDPC码并行译码FPGA实现架构及译码方法，主要包括串并转换模块、输入缓存模块、变量节点更新模块、交织器模块、节点缓存模块和校验节点更新模块。基于DVB-S2标准IRA-LDPC码的准循环特点，在并行译码时的中间计算结果只需要进行列间交织和列内循环移位即可实现二维交织，把二维运算简化为两个一维运算。