Power semiconductor device and method for manufacturing same
The present invention relates to a power semiconductor device and a method for manufacturing the same. The power semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer and a gate electrode disposed on the substrate and disposed between the d...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | chi ; eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | JUN HEE CHO TAE HOON LEE JIN SEONG CHUNG |
description | The present invention relates to a power semiconductor device and a method for manufacturing the same. The power semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer and a gate electrode disposed on the substrate and disposed between the drain region and the source region, a protection layer in contact with a top surface of the substrate and a top surface of the gate electrode, a source contact plug connected to the source region, a drain contact plug connected to the drain region, and a field plate plug in contact with the protection layer, wherein a width of the field plate plug is greater than a width of the source contact plug or a width of the drain contact plug.
本发明涉及功率半导体器件及其制造方法。根据本发明的功率半导体器件包括:布置在基板上的漏极区和源极区;布置在基板上且布置在漏极区与源极区之间的栅极绝缘层和栅电极;与基板的顶表面和栅电极的顶表面接触的保护层;连接至源极区的源极接触插塞;连接至漏极区的漏极接触插塞;以及与保护层接触的场板插塞,其中,场板插塞的宽度大于源极接触插塞的宽度或漏极接触插塞的宽度。 |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN110277441A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN110277441A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN110277441A3</originalsourceid><addsrcrecordid>eNrjZLAJyC9PLVIoTs3NTM7PSylNLskvUkhJLctMTlVIzEtRyE0tychPUUgDiuYm5pWmJSaXlBZl5qUrFCfmpvIwsKYl5hSn8kJpbgZFN9cQZw_d1IL8-NTigsTk1LzUknhnP0NDAyNzcxMTQ0djYtQAAArcMAo</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Power semiconductor device and method for manufacturing same</title><source>esp@cenet</source><creator>JUN HEE CHO ; TAE HOON LEE ; JIN SEONG CHUNG</creator><creatorcontrib>JUN HEE CHO ; TAE HOON LEE ; JIN SEONG CHUNG</creatorcontrib><description>The present invention relates to a power semiconductor device and a method for manufacturing the same. The power semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer and a gate electrode disposed on the substrate and disposed between the drain region and the source region, a protection layer in contact with a top surface of the substrate and a top surface of the gate electrode, a source contact plug connected to the source region, a drain contact plug connected to the drain region, and a field plate plug in contact with the protection layer, wherein a width of the field plate plug is greater than a width of the source contact plug or a width of the drain contact plug.
本发明涉及功率半导体器件及其制造方法。根据本发明的功率半导体器件包括:布置在基板上的漏极区和源极区;布置在基板上且布置在漏极区与源极区之间的栅极绝缘层和栅电极;与基板的顶表面和栅电极的顶表面接触的保护层;连接至源极区的源极接触插塞;连接至漏极区的漏极接触插塞;以及与保护层接触的场板插塞,其中,场板插塞的宽度大于源极接触插塞的宽度或漏极接触插塞的宽度。</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190924&DB=EPODOC&CC=CN&NR=110277441A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190924&DB=EPODOC&CC=CN&NR=110277441A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JUN HEE CHO</creatorcontrib><creatorcontrib>TAE HOON LEE</creatorcontrib><creatorcontrib>JIN SEONG CHUNG</creatorcontrib><title>Power semiconductor device and method for manufacturing same</title><description>The present invention relates to a power semiconductor device and a method for manufacturing the same. The power semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer and a gate electrode disposed on the substrate and disposed between the drain region and the source region, a protection layer in contact with a top surface of the substrate and a top surface of the gate electrode, a source contact plug connected to the source region, a drain contact plug connected to the drain region, and a field plate plug in contact with the protection layer, wherein a width of the field plate plug is greater than a width of the source contact plug or a width of the drain contact plug.
本发明涉及功率半导体器件及其制造方法。根据本发明的功率半导体器件包括:布置在基板上的漏极区和源极区;布置在基板上且布置在漏极区与源极区之间的栅极绝缘层和栅电极;与基板的顶表面和栅电极的顶表面接触的保护层;连接至源极区的源极接触插塞;连接至漏极区的漏极接触插塞;以及与保护层接触的场板插塞,其中,场板插塞的宽度大于源极接触插塞的宽度或漏极接触插塞的宽度。</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAJyC9PLVIoTs3NTM7PSylNLskvUkhJLctMTlVIzEtRyE0tychPUUgDiuYm5pWmJSaXlBZl5qUrFCfmpvIwsKYl5hSn8kJpbgZFN9cQZw_d1IL8-NTigsTk1LzUknhnP0NDAyNzcxMTQ0djYtQAAArcMAo</recordid><startdate>20190924</startdate><enddate>20190924</enddate><creator>JUN HEE CHO</creator><creator>TAE HOON LEE</creator><creator>JIN SEONG CHUNG</creator><scope>EVB</scope></search><sort><creationdate>20190924</creationdate><title>Power semiconductor device and method for manufacturing same</title><author>JUN HEE CHO ; TAE HOON LEE ; JIN SEONG CHUNG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN110277441A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>JUN HEE CHO</creatorcontrib><creatorcontrib>TAE HOON LEE</creatorcontrib><creatorcontrib>JIN SEONG CHUNG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JUN HEE CHO</au><au>TAE HOON LEE</au><au>JIN SEONG CHUNG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Power semiconductor device and method for manufacturing same</title><date>2019-09-24</date><risdate>2019</risdate><abstract>The present invention relates to a power semiconductor device and a method for manufacturing the same. The power semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer and a gate electrode disposed on the substrate and disposed between the drain region and the source region, a protection layer in contact with a top surface of the substrate and a top surface of the gate electrode, a source contact plug connected to the source region, a drain contact plug connected to the drain region, and a field plate plug in contact with the protection layer, wherein a width of the field plate plug is greater than a width of the source contact plug or a width of the drain contact plug.
本发明涉及功率半导体器件及其制造方法。根据本发明的功率半导体器件包括:布置在基板上的漏极区和源极区;布置在基板上且布置在漏极区与源极区之间的栅极绝缘层和栅电极;与基板的顶表面和栅电极的顶表面接触的保护层;连接至源极区的源极接触插塞;连接至漏极区的漏极接触插塞;以及与保护层接触的场板插塞,其中,场板插塞的宽度大于源极接触插塞的宽度或漏极接触插塞的宽度。</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | chi ; eng |
recordid | cdi_epo_espacenet_CN110277441A |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Power semiconductor device and method for manufacturing same |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T17%3A36%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=JUN%20HEE%20CHO&rft.date=2019-09-24&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN110277441A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |