DBC board layout method for reducing parasitic inductance of GaN HEMT power module packaging

The invention relates to a DBC board layout method for reducing the parasitic inductance of GaN HEMT power module packaging, and belongs to the technical field of semiconductor packaging. The DBC board is pasted with components with circuit design layout, wherein the components include a GaN chip, a...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	ZHANG ZHIQING, CAO SHIKUN, GAN KUN, LI SHUAI, ZHANG QIAN, YUAN FENGPO, BAI XINJIAO
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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