DBC board layout method for reducing parasitic inductance of GaN HEMT power module packaging

The invention relates to a DBC board layout method for reducing the parasitic inductance of GaN HEMT power module packaging, and belongs to the technical field of semiconductor packaging. The DBC board is pasted with components with circuit design layout, wherein the components include a GaN chip, an MOS chip, a gate resistor and a power terminal. The DBC board includes a source region, a drain region and a gate region, the GaN chip, the MOS chip, the gate resistor and the DBC board are welded by means of solder paste reflow, and the vacant space reserved among the GaN chip, the MOS chip, the gate resistor and the power terminal is clad copper on the DBC board. According to the invention, the DBC board is reasonably laid out, the parasitic inductance of the clad copper on the surface of the DBC board is improved, the loss caused by the overlarge parasitism of a GaN device in the packaging form at a high frequency is reduced, and the method for packaging the high-frequency GaN power module structure is realize