SUPPRESSION OF PROGRAM DISTURB WITH BIT LINE AND SELECT GATE VOLTAGE REGULATION

Techniques for suppression of program disturb in memory devices are described herein. In an example embodiment, a memory device comprises a flash memory array coupled to a control circuit. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupledto a respective bit line (BL). The control circuit is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory array, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the memory device. 本文描述了用于存储器装置中的编程干扰的抑制的技术。在示例实施例中，存储器装置包括耦合到控制电路的闪存阵列。闪存阵列包括存储器单元的行和列，其中每行中的存储器单元耦合到源极线和选择栅极(SG)线，并且每列中的存储器单元耦合到相应的位线(BL)。控制电路被配置为独立于闪存阵列的电源电压来调节选择的SG线的第一电压和未被选择的BL的第二电压两者，并且基于对存储器装置的操作温度的测量来调整第一电压和第二电压中的至少一个。