Layout and wiring method and device for FPGA online logic analyzer

The invention provides a layout and wiring method and device of an FPGA online logic analyzer. The layout and wiring method for the FPGA online logic analyzer comprises the following steps: when carrying out hardware circuit layout and wiring on an FPGA chip, performing user design layout wiring according to an acquired user design netlist; marking used resources in the process that a user designslayout wiring; then, performing layout and wiring of the online logic analyzer in unmarked resources according to a netlist of the online logic analyzer, to realize layout and wiring on the user design; and then performing layout and wiring on the on-line logic analyzer by utilizing residual resources, so that layout and wiring designed by a user can be preferentially ensured, and meanwhile, theinfluence of the layout and the wiring of the on-line logic analyzer is avoided, so that the layout and the wiring are independent from each other and do not influence each other, and the troubleshooting and solving of the lay