Integrated circuit package having offset vias

Integrated circuit packages comprise vias, each of which extends from a pad in communication with an integrated circuit on a semiconductor chip through insulating material overlying the semiconductorchip to an attachment surface facing a substrate. The portion of each via proximate the attachment su...

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Bibliographische Detailangaben
Hauptverfasser: SU MICHAEL ZHUOYING, LEI FU, KUECHENMEISTER FRANK
Format: Patent
Sprache:chi ; eng
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Beschreibung
Zusammenfassung:Integrated circuit packages comprise vias, each of which extends from a pad in communication with an integrated circuit on a semiconductor chip through insulating material overlying the semiconductorchip to an attachment surface facing a substrate. The portion of each via proximate the attachment surface is laterally offset from the portion proximate the pad from which it extends in a direction away from the centre of the semiconductor chip. Metallic material received in the vias mechanically and electrically interconnects the semiconductor chip to the substrate. 集成电路封装包括通孔,所述通孔中的每一个从与半导体芯片上的集成电路连通的衬垫延伸通过上覆于所述半导体芯片上的绝缘材料至面向衬底的附着面。每个通孔的接近所述附着面的部分横向偏离接近所述衬垫的所述部分,其在远离所述半导体芯片的中心的方向上从所述衬垫延伸。容纳在所述通孔中的金属材料使所述半导体芯片与所述衬底机械地并电气地互连。