CONNECTION WIRING

Provided is connection wiring which suppresses faulty connections between pumps and pads when mounting semiconductor chips, and allows for an increase in the number of pads. In a region sandwiched bya pad row at a particular level and a pad row at a level adjacent to said level, the connection wirin...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: SHIOTA MOTOJI, MURAOKA SEIJI, SHIMIZU YUKIO
Format: Patent
Sprache:chi ; eng
Schlagworte:
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Beschreibung
Zusammenfassung:Provided is connection wiring which suppresses faulty connections between pumps and pads when mounting semiconductor chips, and allows for an increase in the number of pads. In a region sandwiched bya pad row at a particular level and a pad row at a level adjacent to said level, the connection wiring is arranged such that a first wire (31) goes beneath a second wire (32) which is adjacent thereto, and the second wire (32) goes above the first wire (31) which is adjacent thereto. In this case, of the three wires, the wire located in the middle is the first wire (31), and the second wire (32) is disposed so as to sandwich the first wire (31), even in a region sandwiched by pads (20) at any level. The pitch of the pads (20) can thus be made narrower without reducing the width of the pads. 提供一种能在安装半导体芯片时抑制凸点与焊盘的连接不良来使焊盘数增加的连接用配线。在夹在任何的级的焊盘列与同该级相邻的级的焊盘列之间的区域,配置为:第一配线(31)从相邻的第二配线(32)的下方穿过或第二配线(32)从相邻的第一配线(31)的上方跨过。在这种情况下,在夹在任何的级的焊盘(20)与焊盘(20)之间的区域,三根配线中配置于中央的配线为第一配线(31),第二配线(32)配置为将第一配线(31)夹住。由此,不缩窄焊盘(20)的宽度就能将焊盘(2