INTERFACE CIRCUIT FOR MULTI RANK MEMORY

The application provides an electronic circuit for a multi rank memory. The circuit includes a first delay line circuit to generate a first data strobe by delaying a second data strobe, such that an edge of the first data strobe is aligned within a first time interval; and a sampling circuit to sample the first data signal at the edge of the first data strobe, wherein plural data signals include the first data signal and a second data signal, wherein timings of the plural data signals deviate from a reference timing of a reference data strobe by plural time lengths, wherein the first data signal deviates from the reference timing by a first time length of the plural time lengths, and wherein an edge of the second data strobe is aligned within a second time interval, wherein a timing of thesecond data signal deviates from the reference timing by a shortest time length of the plural time lengths. 本申请提供一种用于多区块存储器的接口电路。所述电路包括：第一延迟线电路，其通过延迟第二数据选通来产生第一数据选通，以使得所述第一数据选通的边沿在第一时间间隔中对齐；以及采样电路，其在所述第一数据选通的边沿对所述第一数据信号采样，其中