MULTI LEVEL SYSTEM MEMORY HAVING DIFFERENT CACHING STRUCTURES AND MEMORY CONTROLLER THAT SUPPORTS CONCURRENT LOOK-UP INTO THE DIFFERENT CACHING STRUCTURES

An apparatus is described. The apparatus includes a memory controller to interface to a multi- level system memory having first and second different cache structures. The memory controller has circuitry to service a read request by concurrently performing a look-up into the first and second different cache structures for a cache line that is targeted by the read request. 描述一种设备。该设备包括通过接口连接到具有第一和第二不同高速缓存结构的多级系统存储器的存储器控制器。存储器控制器具有通过对于由读取请求所针对的高速缓存行在第一和第二不同高速缓存结构中并发执行查找而服务于读取请求的电路。