Wafer-level package with enhanced performance

The present disclosure relates to a wafer-level package that includes a first thinned die (12), a multilayer redistribution structure (18), a first mold compound (20), and a second mold compound (22).The first thinned die resides over a top surface of the multilayer redistribution structure. The mul...

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Bibliographische Detailangaben
Hauptverfasser: HAMMOND JONATHAN HALE, CHADWICK JON, HATCHER JR MERRILL ALBERT, COSTA JULIO C, VANDEMEER JAN EDWARD
Format: Patent
Sprache:chi ; eng
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Zusammenfassung:The present disclosure relates to a wafer-level package that includes a first thinned die (12), a multilayer redistribution structure (18), a first mold compound (20), and a second mold compound (22).The first thinned die resides over a top surface of the multilayer redistribution structure. The multilayer redistribution structure includes at least one support pad (52(1)) that is on a bottom surface of the multilayer redistribution structure and vertically aligned with the first thinned die. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening (54) within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die. 本公开涉及一种晶片级封装,所述晶片级封装包括第一薄化裸片(12)、多层再分布结构(18)、第一模化合物(20)以及第二模化合物(22)。所述第一薄化裸片驻留在所述多层再分布结构的顶部表面上方。所述多层再分布结构包括至少一个支撑垫(52(1)),所述至少一个支撑垫在所述多层再分布结构的底部表面上并且与所述第一薄化裸片垂直地