A method and a device for improving the NOR type memory array reading speed
The invention discloses a method and device for improving the NOR type storage array reading speed. The method comprises the steps of dividing an NOR type storage array into 2n sub-arrays; If first reading is carried out, determining an address of a selected bit line and an address of a selected wor...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention discloses a method and device for improving the NOR type storage array reading speed. The method comprises the steps of dividing an NOR type storage array into 2n sub-arrays; If first reading is carried out, determining an address of a selected bit line and an address of a selected word line according to the first address, and carrying out reading operation on the storage units in the 2n sub-arrays at the same time according to the address of the selected bit line, the address of the selected word line, the state of a bit line address identification bit and the state of a regional molecular array identification bit in the bit line address identification bit; And if not, outputting data corresponding to the address of the current selected word line and the storage unit corresponding to the address of the current selected bit line, and carrying out reading operation on the storage unit of the next sub-array. According to the technical scheme provided by the embodiment of the invention, the storage |
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