testing device for a memory chip in a hybrid circuit

The invention provides a testing device for a memory chip in a hybrid circuit. capable of achieving fault positioning and diagnosis at the same time; The device comprises a built-in self-test circuitand a bus multiplexing circuit. The built-in self-test circuit and the bus multiplexing circuit are arranged on the main control protocol chip; The built-in self-test circuit is connected with a selection signal port of the bus multiplexing circuit. The built-in self-test circuit is connected with the bus multiplexing circuit through the test mode control bus, the test mode address bus and the test mode data bus. The main control protocol chip also comprises a functional memory controller; Wherein a control bus of the main control protocol chip is connected with a control port of the memory chip, a data bus of the main control protocol chip is connected with a data port of the memory chip, and an address bus of the main control protocol chip is connected with an address port of the memorychip; An output data bus o