SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

The present invention improves the detection accuracy of a timing error in a semiconductor integrated circuit provided with a storage element that operates in synchronization with a clock signal. A delay unit delays a data signal by two delay times different from each other and outputs resultant signals as first and second delayed signals. A holding unit holds the first and second delayed signalsin synchronization with a timing signal indicating predetermined capture timing. A setup time detection unit detects whether or not one of the first and second delayed signals held within a setup time-side detection period from predetermined start timing to the predetermined capture timing has changed. A hold time detection unit detects whether or not the other of the first and second delayed signals held within a hold time-side detection period from the predetermined capture timing to predetermined end timing has changed. 本发明提高了设置有与时钟信号同步操作的存储器件的半导体集成电路中的时序误差精度。延迟部使数据信号延迟相互不同的两个延迟时间，并且将得到的信号输出为第一和第二延迟信号。保持部与指示预定的捕获时序