Clock generation control circuit and control system

The invention discloses a clock generation control circuit, and the circuit comprises a frequency multiplying circuit and a duty ratio circuit. The output end of the frequency multiplying circuit is connected with the input end of the duty ratio circuit, and the frequency multiplying circuit processes a received external input signal into a frequency multiplying signal, and transmits the frequencymultiplying signal to the duty ratio circuit. The duty ratio circuit calibrates the frequency multiplying signal and outputs a clock signal. According to the invention, the circuit realizes the spreading and calibration of the clock signal through the relatively independent frequency multiplying circuit and the duty ratio circuit, thereby outputting a continuous clock signal. At the same time, the circuit of the invention is simple in design and is lower in power consumption. The present invention also provides a clock generation control system. 本发明公开了种时钟产生控制电路，包括倍频电路和占空比电路，倍频电路的输出端与占空比电路的输入端连接；倍频电路将接收的外部输入信号处理为倍频信号，