Trigger and chip

The embodiment of the present application provides a trigger and a chip. The trigger includes an error correction circuit and an error detection circuit; wherein the first input end of the error correction circuit serves as a data input end of the trigger; the output end of the error correction circuit is connected to the first input end of the error detection circuit; the second input end of theerror detection circuit serves as a clock input end of the trigger; and the output end of the error detection circuit is connected to the second input end and the third input end of the error correction circuit. The error detection circuit is configured to send an error correction signal to the error correction circuit when detecting that the trigger generates a single event upset (SEU). The errorcorrection circuit is configured to subject the trigger to error correction processing when receiving the error correction signal. It can be seen that, on the basis of an error correction function, the working state of the tr