FPGA implementation method using SAR echo data pre-filtering technology

The invention relates to an FPGA implementation method using SAR echo data pre-filtering technology, and belongs to the technical field of radar imaging and the technical field of digital signal processing. The method comprises the following steps of 1, determining the order of a filter; 2, storing the echo data in a DDR in the form of a two-dimensional matrix, wherein the size of the two-dimensional matrix is obtained by multiplying the order of the filter by a point number of range direction, and when the number of pulses is greater than the order of the filter, overwriting the previous echodata from the start position of the matrix; 3, when a piece of pulse data is stored, calculating the sum of elements in a current matrix by using a fast algorithm, namely the output of the first-order filter; 4, using the output of the first-order filter as an input and repeating the steps 2 and 3 to form a second-stage filter; and 5, sampling the output of the second-stage filter proportionallyand then outputting and st