LOW-POWER DATA BUS RECEIVER

The present invention relates to a circuit for receiving and processing a bit stream obtained from an electronic communication bus-system. The circuit comprises a bit stream processing unit for synchronization and bit sampling of the bit stream to provide a sampled output signal. The circuit comprises a frame decoding unit for decoding a data frame encoded in the sampled output signal. The circuitcomprises a clock signal generator for generating a first clock signal for the bit stream processing unit. The circuit comprises a clock signal downsampler for generating a second clock signal havinga lower frequency than the first clock signal, in which the second clock signal is based on a cooccurrence of a clock pulse in the first clock signal and the emission of a bit in the sampled output signal. The second clock signal is provided to the frame decoding unit. The bit stream processing unit is adapted for synchronizing the first clock signal to an external protocol timing of the incomingbit stream. 本发明涉及种用于对从电子通信