Method and system for determining consistency between codes and integrated circuits of FPGA redundancy design

The invention belongs to the technical field of nuclear electricity control and provides a method and system for determining consistency between codes and integrated circuits of FPGA redundancy designwith the intent of resolving the defects of an integration and simulation method and an formalized consistency verification method in the prior art. The method comprises the following steps: S1: respectively retrieving a first keyword of FPGA codes and a second keyword, corresponding to a netlist file, of the integrated circuits; S2, judging whether a first signal name set acquired by retrievingthe first keyword in the FPGA codes belongs to a subset of a second signal name set acquired by retrieving the second keyword in the netlist file or not; if so, passing a consistency test of signals of the integrated circuits; S3, determining whether one or multiple useful logic units in the netlist file corresponding to the integrated circuits are connected with signals of an announcement of an FPGA code file or not; if s