MEMORY CIRCUIT WITH LEAKAGE COMPENSATION

In a memory array comprising a word line and a bit line, each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell (400, 402) of the plurality of memory ce...

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Bibliographische Detailangaben

Hauptverfasser:	RAO RAVIPRAKASH SURYANARAYANA, HEINRICH-BARNA STEPHEN KEITH
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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