MEMORY CIRCUIT WITH LEAKAGE COMPENSATION

In a memory array comprising a word line and a bit line, each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell (400, 402) of the plurality of memory cells has the second terminal coupled to receive a first supply voltage (Vss) when selected by the word line. A second memory cell (404, 406) of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage (Vdd-Vtn) when the first memory cell (400, 402) is selected by the word line. 在包括字线和位线的存储器阵列中，存储器阵列的多个存储器单元中的每个具有连接到位线的第端子和在第端子与相应的第二端子之间的电流路径。多个存储器单元中的第存储器单元(400,402)具有第二端子，其经耦合以在被字线选择时接收第电源电压(Vss)。多个存储器单元中的第二存储器单元(404,406)具有第二端子，其经耦合以在第存储器单元(400,402)被字线选择时接收与第电源电压不同的电压(Vdd-Vtn)。