Low-dark-count-rate CMOS SPAD photoelectric device

The invention provides a low-dark-count-rate CMOS SPAD photoelectric device. A P-well layer is added based on a routine P+/N-well type SPAD structure. The P-well layer is arranged between the P+ layerand the N-well layer. Furthermore, an N-well clearance is utilized as a virtual protecting ring of the structure; namely N-wells are added at two sides of a PN junction, wherein the structure is shown in the attached figures of an abstract. An incident photon is incident into the device and is attracted at the central N well, and furthermore a photon-generated carrier is generated. The P-well layer and the N-well layer are utilized at two sides of the PN junction. Hereon an avalanche junction is a P-well/N-well junction. Because the avalanche junction is a lightly doped avalanche junction, width of a depletion region increases, and probability of interband tunneling of the carries is reduced, thereby reducing the dark counting rate. Furthermore the virtual protecting ring is used for suppressing edge breakdown of