Layout structure and method for specific integrated circuit chip

The embodiment of the invention provides a layout structure for a specific integrated circuit chip. The layout structure comprises a computation kernel region and input and output regions, wherein thecomputation kernel region comprises arrays composed by multiple logical unit blocks, the arrays composed by the multiple logical unit blocks comprise two lines which are symmetrical left and right, multiple rows exist in each line, and a logical unit block is arranged in each row; the input and output region include the first input output region arranged on the first edge of the specific integrated circuit chip and the second input output region arranged on the second edge, opposite to the first edge, of the specific integrated circuit chip, and the first input output region and the second input output region each comprises at least one input output unit parallelly arranged; a middle channel is formed between the arrays symmetrical left and right, and is used for wiring a signal transmission line connecting the f