Automatic identification wafer box for side sealing of integrated circuit

The invention discloses an automatic identification wafer box for side sealing of an integrated circuit. The wafer box is of a cuboid structure comprising a top plate, a bottom plate, a left side plate, a right side plate and a rear cover plate, wherein wafer grooves are formed in the left side plate and the right side plate, a front surface of the wafer box is opened, wafer grooves are formed ininner walls of the left side plate and the right side plate, three V-shaped positioning mechanisms are arranged below the bottom plate, push-rod type automatic padlock structures are arranged on the bottom plate and the side plates of the wafer box, three clamping groove-type baffle strips are respectively arranged on the left side plate, the right side plate and the rear cover plate of the waferbox, and an automatic identification matrix is arranged on the top of the wafer box. By the automatic identification wafer box, the influence of manual operation on cleanness of the wafer can be prevented, the probably that tw