Boolean logic in a state machine lattice

The application relates to a boolean logic in a state machine lattice. Disclosed are methods and devices, among which is a device that includes a finite state machine lattice (30). The lattice (30) may include a programmable Boolean logic cell (58B) that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Booleanlogic cell (58B), an inversion of a last output of the Boolean logic cell (58B), and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell (58B). The Boolean logic cell(58B) also includes an end of data circuitry configured to cause the Boolean logic cell (58B) to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell (58B). 本申请涉及状态机晶格中的布尔逻辑。在个实施例中揭示若干方法及装置，其中存在种包含有限状态机晶格(30)的装置。所述晶格(30)可包含可经编程以对数据流执行各种逻辑函数的可编程布尔逻辑单元(58B)。所述可编程性包含到所述布尔逻辑单元(58B)的第输入的反相、所述布尔逻辑单元(58B)的最后输出的反相及"与"门或者"或"门作为所述布尔逻辑单元(58B)的最终输出的选择。所述布尔逻辑单元(58B)还包含经配置以致使所述布尔逻辑单元