3D staggered floor stacked packaging structure for bulk memory circuit

The invention discloses a 3D staggered floor stacked packaging structure for a bulk memory circuit, and belongs to the technical field of electronic product packaging. The structure comprises memory chips, an adhesive, bonding wires, a substrate, and a housing. The structure is provided with a plurality of memory chips, and a 3D chip group is formed in a vertical staggered stacking mode, wherein the memory chips are bonded through the adhesive. The3D chip group is bonded on the substrate through the adhesive, and the substrate is fixed on the housing through the adhesive. The binding wires areused for achieving the electrical connection between the 3D chip group and the substrate, between the 3D chip group and the housing, and between the memory chips. According to the invention the chipsare arranged in the vertical staggered stacking mode, thereby improving the storage capacity, and meeting the high-reliability demands of a domestic cutting-edge industry for the memory products. 本发明公开了种大容量存储器电路的3D错层堆叠封装结构，属于