Threshold voltage adjustment for a gate-all-around semiconductor structure

A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids. The embodiment of the invention also relates to threshold voltage adjustment for a gate-all-around semiconductor structure. 半导体结构包括与多个第二半导体层交错的多个第半导体层。第半导体层和第二半导体层具有不同的材料组分。在最上第半导体层上方形成伪栅极堆叠件。实施第蚀刻工艺以去除未设置在伪栅极堆叠件下面的第二半导体层的部分，从而形成多个空隙。第蚀刻工艺在第半导体层和第二半导体层之间具有蚀刻选择性。之后，实施第二蚀刻工艺以扩大空隙。本发明的实施例还涉及用于全环栅半导体结构的阈值电压调整。