Method of reducing transistor fabrication steps

The present invention discloses a method for reducing transistor fabrication steps. The method includes the following steps that: step 1, an initial transistor is prepared and is adopted as a mother set for replication; step 2, the structure of the mother set is replicated, so that a replication mold is obtained; step 3, a mould pressing substrate is prepared, wherein the mould pressing substrateis sequentially provided with an adhesive, polycrystalline silicon, silicon oxide, silicon and a substrate from top to bottom; step 4, the mould pressing substrate prepared in the step 3 and the replication mold obtained in the step 2 are subjected to mould pressing, so that the three-dimensional structure of the adhesive can be obtained; step 5, pattern transfer is performed on the three-dimensional structure of the adhesive by means of the etching of reactive ions; and step 6, the adhesive is removed, and doping is performed, and a transistor is obtained. With the method for reducing transistor fabrication steps ado