SRAM reading-writing circuit and SRAM data accessing method

The invention relates to an SRAM reading-writing circuit and an SRAM data accessing method. The circuit comprises an address/data control module, an address displacement chain, a data displacement chain and an SRAM memorizer array. The address/data control module receives clock signals and serial data and is used for coding the serial data in the clock signals and outputting a displacement instruction. The address displacement chain is connected to the address/data control module and used for receiving the displacement instruction of the address/data control module to conduct an address displacement operation. The data displacement chain is connected to the address/data control module and used for receiving a displacement enabling signal of the address/data control module to conduct a datadisplacement operation or used for transmitting the serial data of SRAM memorizers. The SRAM memorizer array is connected to the address displacement chain and the data displacement chain. The generation of a reading-writing