RANDOM CLOCK GENERATOR

The invention relates to a random clock generator comprising an input receiving a master clock signal MCIk, and a clock signal reduction circuit (101) receiving the master clock signal MCIk and a whole number N and supplying an output signal corresponding to a train of N pulses every M clock pulse,...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: PEREZ CHAMORRO JORGE ERNESTO, LOUBET MOUNDI PHILIPPE, COULON JEAN-ROCH
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator PEREZ CHAMORRO JORGE ERNESTO
LOUBET MOUNDI PHILIPPE
COULON JEAN-ROCH
description The invention relates to a random clock generator comprising an input receiving a master clock signal MCIk, and a clock signal reduction circuit (101) receiving the master clock signal MCIk and a whole number N and supplying an output signal corresponding to a train of N pulses every M clock pulse, M being a whole number higher than 1 and N being a whole number higher than 1 and lower than or equal to M. A number generator (102) and (103) supplies a new number (N) to the clock signal reduction circuit every P pulse of a master clock signal, N and/or P being produced randomly. 本发明涉及种随机时钟生成器,其包括接收主时钟信号MClk的输入和接收主时钟信号MClk和整数N并且提供输出信号的时钟信号缩减电路(101),所述输出信号对应于每M个时钟脉冲的串N个脉冲,M是大于1的整数并且N是大于1且小于或等于M的整数。数字生成器(102)和(103)每主时钟信号的P个脉冲向时钟信号缩减电路提供新的数字(N),N和/或P是随机产生的。
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN108027719A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN108027719A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN108027719A3</originalsourceid><addsrcrecordid>eNrjZBALcvRz8fdVcPbxd_ZWcHf1cw1yDPEP4mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hgYWBkbm5oaWjsbEqAEArUAfFw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>RANDOM CLOCK GENERATOR</title><source>esp@cenet</source><creator>PEREZ CHAMORRO JORGE ERNESTO ; LOUBET MOUNDI PHILIPPE ; COULON JEAN-ROCH</creator><creatorcontrib>PEREZ CHAMORRO JORGE ERNESTO ; LOUBET MOUNDI PHILIPPE ; COULON JEAN-ROCH</creatorcontrib><description>The invention relates to a random clock generator comprising an input receiving a master clock signal MCIk, and a clock signal reduction circuit (101) receiving the master clock signal MCIk and a whole number N and supplying an output signal corresponding to a train of N pulses every M clock pulse, M being a whole number higher than 1 and N being a whole number higher than 1 and lower than or equal to M. A number generator (102) and (103) supplies a new number (N) to the clock signal reduction circuit every P pulse of a master clock signal, N and/or P being produced randomly. 本发明涉及种随机时钟生成器,其包括接收主时钟信号MClk的输入和接收主时钟信号MClk和整数N并且提供输出信号的时钟信号缩减电路(101),所述输出信号对应于每M个时钟脉冲的串N个脉冲,M是大于1的整数并且N是大于1且小于或等于M的整数。数字生成器(102)和(103)每主时钟信号的P个脉冲向时钟信号缩减电路提供新的数字(N),N和/或P是随机产生的。</description><language>chi ; eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; PULSE TECHNIQUE</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20180511&amp;DB=EPODOC&amp;CC=CN&amp;NR=108027719A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20180511&amp;DB=EPODOC&amp;CC=CN&amp;NR=108027719A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PEREZ CHAMORRO JORGE ERNESTO</creatorcontrib><creatorcontrib>LOUBET MOUNDI PHILIPPE</creatorcontrib><creatorcontrib>COULON JEAN-ROCH</creatorcontrib><title>RANDOM CLOCK GENERATOR</title><description>The invention relates to a random clock generator comprising an input receiving a master clock signal MCIk, and a clock signal reduction circuit (101) receiving the master clock signal MCIk and a whole number N and supplying an output signal corresponding to a train of N pulses every M clock pulse, M being a whole number higher than 1 and N being a whole number higher than 1 and lower than or equal to M. A number generator (102) and (103) supplies a new number (N) to the clock signal reduction circuit every P pulse of a master clock signal, N and/or P being produced randomly. 本发明涉及种随机时钟生成器,其包括接收主时钟信号MClk的输入和接收主时钟信号MClk和整数N并且提供输出信号的时钟信号缩减电路(101),所述输出信号对应于每M个时钟脉冲的串N个脉冲,M是大于1的整数并且N是大于1且小于或等于M的整数。数字生成器(102)和(103)每主时钟信号的P个脉冲向时钟信号缩减电路提供新的数字(N),N和/或P是随机产生的。</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBALcvRz8fdVcPbxd_ZWcHf1cw1yDPEP4mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hgYWBkbm5oaWjsbEqAEArUAfFw</recordid><startdate>20180511</startdate><enddate>20180511</enddate><creator>PEREZ CHAMORRO JORGE ERNESTO</creator><creator>LOUBET MOUNDI PHILIPPE</creator><creator>COULON JEAN-ROCH</creator><scope>EVB</scope></search><sort><creationdate>20180511</creationdate><title>RANDOM CLOCK GENERATOR</title><author>PEREZ CHAMORRO JORGE ERNESTO ; LOUBET MOUNDI PHILIPPE ; COULON JEAN-ROCH</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN108027719A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2018</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>PEREZ CHAMORRO JORGE ERNESTO</creatorcontrib><creatorcontrib>LOUBET MOUNDI PHILIPPE</creatorcontrib><creatorcontrib>COULON JEAN-ROCH</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PEREZ CHAMORRO JORGE ERNESTO</au><au>LOUBET MOUNDI PHILIPPE</au><au>COULON JEAN-ROCH</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>RANDOM CLOCK GENERATOR</title><date>2018-05-11</date><risdate>2018</risdate><abstract>The invention relates to a random clock generator comprising an input receiving a master clock signal MCIk, and a clock signal reduction circuit (101) receiving the master clock signal MCIk and a whole number N and supplying an output signal corresponding to a train of N pulses every M clock pulse, M being a whole number higher than 1 and N being a whole number higher than 1 and lower than or equal to M. A number generator (102) and (103) supplies a new number (N) to the clock signal reduction circuit every P pulse of a master clock signal, N and/or P being produced randomly. 本发明涉及种随机时钟生成器,其包括接收主时钟信号MClk的输入和接收主时钟信号MClk和整数N并且提供输出信号的时钟信号缩减电路(101),所述输出信号对应于每M个时钟脉冲的串N个脉冲,M是大于1的整数并且N是大于1且小于或等于M的整数。数字生成器(102)和(103)每主时钟信号的P个脉冲向时钟信号缩减电路提供新的数字(N),N和/或P是随机产生的。</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_CN108027719A
source esp@cenet
subjects BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
PULSE TECHNIQUE
title RANDOM CLOCK GENERATOR
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-25T02%3A28%3A39IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=PEREZ%20CHAMORRO%20JORGE%20ERNESTO&rft.date=2018-05-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN108027719A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true