RANDOM CLOCK GENERATOR

The invention relates to a random clock generator comprising an input receiving a master clock signal MCIk, and a clock signal reduction circuit (101) receiving the master clock signal MCIk and a whole number N and supplying an output signal corresponding to a train of N pulses every M clock pulse, M being a whole number higher than 1 and N being a whole number higher than 1 and lower than or equal to M. A number generator (102) and (103) supplies a new number (N) to the clock signal reduction circuit every P pulse of a master clock signal, N and/or P being produced randomly. 本发明涉及种随机时钟生成器，其包括接收主时钟信号MClk的输入和接收主时钟信号MClk和整数N并且提供输出信号的时钟信号缩减电路（101），所述输出信号对应于每M个时钟脉冲的串N个脉冲，M是大于1的整数并且N是大于1且小于或等于M的整数。数字生成器（102）和（103）每主时钟信号的P个脉冲向时钟信号缩减电路提供新的数字（N），N和/或P是随机产生的。