Chip packaging structure

The invention discloses a chip packaging structure. The chip packaging structure comprises a substrate and a first chip, a buffer layer and a second chip which are stacked on one side of the substratein turn, wherein the vertical projection of the buffer layer on the substrate and the vertical projection of the second chip on the substrate are within the vertical projection of the first chip on the substrate; and a power welding pad which is arranged on the surface of one side away from the substrate of the first chip, wherein all or partial vertical projection of the power welding pad on thesubstrate is within the vertical projection of the second chip on the substrate, and the power welding pad is directly or indirectly electrically connected with the substrate through a lead so that the substrate is enabled to supply power to the first chip. According to the technical scheme, the effects of reducing the packaging size and enlarging the wiring range can be realized. 本发明公开了种芯片封装结构，该芯片封装结构包括基板，依次堆叠于所述基板侧的第芯片、