Embedded sige process for multi-threshold pmos transistors

In described examples of an integrated circuit and method having a first PMOS transistor (205) with extension (210) and pocket implants (212) and with SiGe source and drains (230) and having a secondPMOS transistor (215) without extension and without pocket implants and with SiGe source and drains (...

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Bibliographische Detailangaben
Hauptverfasser:	RILEY DEBORAH J, CHOI YOUNSUNG
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	In described examples of an integrated circuit and method having a first PMOS transistor (205) with extension (210) and pocket implants (212) and with SiGe source and drains (230) and having a secondPMOS transistor (215) without extension and without pocket implants and with SiGe source and drains (230), the distance (C2Gd) from the SiGe source and drains (230) to the gate of the first PMOS transistor (205) is greater than the distance (C2Gu) from the SiGe source and drains (230) to the gate of the second PMOS transistor (215), and the turn on voltage of the first PMOS transistor (205) is atleast 50 mV higher than the turn on voltage of the second PMOS transistor (215). 在所描述的具有第PMOS晶体管(205)和第二PMOS晶体管(215)的集成电路和方法的示例中，第PMOS晶体管(205)具有延伸区(210)和袋区注入物(212)并且具有SiGe源极和漏极(230)，第二PMOS晶体管(215)不具有延伸区且不具有袋区注入物而具有SiGe源极和漏极(230)，第PMOS晶体管(205)的从SiGe源极和漏极(230)到栅极的距离(C2Gd)比第二PMOS晶体管(215)的从SiGe源极和漏极(230)到栅极的距离(C2Gu)大，并且第PMOS晶体管(205)的导通电压比第二PMOS晶体管(215)的导通电压高至少50mV。