Switched capacitance amplifier detuning elimination structure
The invention discloses a switched capacitance amplifier detuning elimination structure, the switched capacitance amplifier detuning elimination structure comprises an operational amplifier AMP, a sampling capacitor C1, a holding capacitor C2, a detuning storage capacitor Cos and eight CMOS switches...
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| Hauptverfasser: | , , , , |
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| Format: | Patent |
| Sprache: | chi ; eng |
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| Zusammenfassung: | The invention discloses a switched capacitance amplifier detuning elimination structure, the switched capacitance amplifier detuning elimination structure comprises an operational amplifier AMP, a sampling capacitor C1, a holding capacitor C2, a detuning storage capacitor Cos and eight CMOS switches; the sampling capacitor C1, the holding capacitor C2 and the detuning storage capacitor Cos are allPIP capacitors; and the operational amplifier AMP is a classical cascode structure amplifier. The difference between the detuning elimination structure provided by the invention and the structures ofthe past is that a detuning storage process of the detuning elimination structure provided by the invention is not required to be consistent with a sampling process, and the detuning storage is onlyrequired to be completed before coming of a holding process. In cooperation with corresponding timing sequence control, the operational amplifier AMP used in the detuning elimination structure provided by the invention can be i |
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