Multi-Threaded Translation And Transaction Re-Ordering For Memory Management Units

Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel. 系统及方法涉及在多线程存储器管理单元MMU中执行地址转换。两个或多于两个地址转换请求可由所述多线程MMU接收且被并行地处理以检索到系统存储器的地址的地址转换。如果所述地址转换存在于所述多线程MMU的转换高速缓冲存储器中，那么可从所述转换高速缓冲存储器接收所述地址转换且将其调度以用于使用所述经转换地址接入所述系统存储器。如果所述转换高速缓冲存储器中存在未命中，那么可在两个或多于两个转换表查核行程中并行地调度两个或多于两个地址转换请求。