In-situ MIS gate structure normally-closed GaN-base transistor and preparation method therefor
The invention relates to the field of semiconductor devices, discloses an in-situ MIS gate structure normally-closed GaN-base transistor and a preparation method, and specifically relates to an improvement method for an MIS interface. The device comprises a substrate, an epitaxial layer, a gate medi...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention relates to the field of semiconductor devices, discloses an in-situ MIS gate structure normally-closed GaN-base transistor and a preparation method, and specifically relates to an improvement method for an MIS interface. The device comprises a substrate, an epitaxial layer, a gate medium layer, a source electrode, a drain electrode and a gate electrode, wherein the epitaxial layer, the gate medium layer, the source electrode, the drain electrode and the gate electrode are disposed on the substrate. The epitaxial layer comprises a stress buffering layer, a GaN layer and an AlGaN barrier layer, and a groove gate structure is formed through etching. The regional growth of a secondary epitaxial GaN layer and an SiN medium layer is selected to form an in-situ growth GaN/SiN interface. Gate medium is deposited on a groove trench gate medium layer, and two ends of the gate electrode are covered by metal to form the source electrode and the drain electrode. The device is simple and reliable in structure |
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