BUS-BIT-ORDER ASCERTAINMENT

Embodiments described include a memory controller (24) for use with a memory device (38a, 38b) that has a plurality of memory-device terminals (36) having respective unique bit significances. The memory controller includes (i) a plurality of external terminals (34), each one of the external terminal...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	ISACHAR ORI, LAZMI TAL, SEMO GIL, KUSHTAI GUY
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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