BUS-BIT-ORDER ASCERTAINMENT

Embodiments described include a memory controller (24) for use with a memory device (38a, 38b) that has a plurality of memory-device terminals (36) having respective unique bit significances. The memory controller includes (i) a plurality of external terminals (34), each one of the external terminals configured to be in communication with a respective one of the memory-device terminals, (ii) a plurality of internal terminals (32) having respective unique bit significances, (iii) a switching unit (26), and (iv) a processor (22). The processor is configured to drive the memory device to communicate a predetermined sequence of bit patterns (44_1-44_8) to the controller, and, in response to the sequence of bit patterns, drive the switching unit to connect each one of the external terminals toa respective one of the internal terminals having the bit significance of the memory-device terminal with which the external terminal is in communication. 所述实施方案包括与具有多个存储器设备端子(36)的存储器设备(38a,38b)起使用的存储器控制器(24)，该多个存储器设备端子具有相应的唯