Decoder using low-density parity-check code and memory controller

The application provides a decoder and a memory controller including the same. The decoder includes a channel mapper configured to generate a plurality of channel reception values based on hard decision information and soft decision information, a strong error detector configured to determine whether a strong error has occurred using a plurality of check node messages and the channel reception values and to correct the channel reception values according to a determination result to produce corrected channel reception values, a variable node unit configured to generate a plurality of variable node messages using the check node messages and the corrected channel reception values, and a check node unit configured to generate the check node messages using the variable node messages. The variable node unit includes a plurality of variable nodes and the check node unit includes a plurality of check nodes. 本申请提供种解码器和包括该解码器的存储控制器。该解码器包括：通道映射器，其配置为基于硬判决信息和软判决信息生成多个通道接收值；强错误检测器，其配置为使用多个校验节点消息和通道接收值确定强错误是否发生，并且根据确定结果校正通