D flip-flop

The invention provides a D flip-flop. The D flip-flop comprises a combinational logical structure used for remaining a high potential of an internal clock signal unchanged and remaining a low potential of an inversion signal of the internal clock signal unchanged when the potential of a data signal and an output signal is the same, and making the internal clock signal change with an external clock signal when the potential of the data signal and the output signal is different; an internal clock control structure, which is connected with the combinational logical structure and used for transmitting the data signal and an inversion signal of the data signal; a differential structure, which is connected with the internal clock control structure and used for compensating a threshold loss caused by high level transmission of an NMOS transistor; a latch structure, which is connected with the internal clock control structure and used for caching the output signal and an inversion signal of the output signal; and an